A new Linux kernel patch from AMD engineers reveals the company is preparing to introduce a third tier of CPU core — explicitly labeled “Low Power” — in future Ryzen processors. The patch, which extends the x86 topology enumeration in the kernel’s ACPI driver, makes room for a new “CPU_ACPI_TYPE_LOW_POWER” core type, sitting alongside the existing “performance” and “efficiency” classifications. For Windows enthusiasts, this low-level code change telegraphs that AMD’s hybrid CPU strategy is about to get far more nuanced, with direct implications for battery life, thermals, and task scheduling on next-generation laptops and handhelds.

The code, posted on the Linux kernel mailing list (LKML) in late June 2024, does not reference specific product names or launch dates. However, such patches rarely emerge out of the blue; they almost always foreshadow silicon that will ship within the next 12 to 18 months. The addition of a dedicated low-power core type signals that AMD is eyeing a heterogeneous architecture with three distinct performance tiers, moving beyond the current big-core / dense-core dichotomy seen in its Ryzen 7040 and 8040 mobile processors.

The Patch: A New Core Type Emerges

At the heart of the change is a simple but telling modification to the kernel’s “topology.c” file. Today, the code recognizes two ACPI-defined CPU types: type 0 for performance cores (typically the “full-fat” Zen cores) and type 1 for efficiency cores (such as the compact Zen 4c or Zen 5c cores). The AMD-authored patch adds a third enumeration: type 2, designated “Low Power.” This new label is not just a renamed efficiency category; it’s a separate identity that the OS scheduler can use to treat cores with markedly different power and performance characteristics.

The patch also introduces the necessary strings and macros so that tools like “sysfs” and “lscpu” can report the core type to userspace applications. That’s crucial because it means heterogeneity-aware software — including hypervisors, container runtimes, and eventually Windows through its WSL2 kernel — can make smarter decisions about where to place workloads. For instance, a web browser’s background tabs could be pinned to low-power cores, while an active video render stays on performance cores, and an always-on voice assistant hums on a dedicated ultra-low-power island.

AMD’s Hybrid Journey So Far

AMD’s trip into heterogeneous computing began quietly with the Ryzen 7 5800U “Cezanne” in 2021, which offered a power-sipping 1.8 GHz base frequency but no distinct core types. The real pivot came with the Zen 4c and Zen 5c “dense” cores, which pack the same instruction-set capabilities into a smaller silicon footprint and lower clock ceiling. In the Ryzen 7040 series “Phoenix,” AMD mixed two Zen 4 performance cores with four Zen 4c efficiency cores in a single package, while higher-end SKUs went all-in on Zen 4. Later, the Ryzen 8040 “Hawk Point” refined this formula.

Throughout this evolution, AMD’s silicon has benefited from Windows 11’s heterogeneous scheduling policy, which uses ACPI CPPC (Collaborative Processor Performance Control) hints to favor performance cores for foreground tasks and efficiency cores for background threads. But that policy only recognizes two tiers. A third tier would force both Microsoft and AMD to rethink how the OS classifies workloads. It could lead to a scheduling scheme where low-power cores handle only the most latency-insensitive, background, or always-on functions — think OS telemetry, wallpaper slideshows, or messaging app syncs — while performance and efficiency cores ramp up for user-interactive and compute-bound tasks respectively.

What Are “Low Power” Cores?

AMD has not detailed what microarchitecture will serve as the basis for its low-power cores, but the Linux patch provides architectural clues. By explicitly separating “Low Power” from “Efficiency,” AMD suggests the new cores will have much lower minimum power states and clock frequencies than even Zen 4c/5c cores. They might be designed to run at fractions of a watt, enabling fanless operation in tablet or convertible form factors, or to extend battery life on handheld gaming PCs by handling OS housekeeping while the APU’s GPU and performance cores are briefly idle.

One compelling possibility is that these low-power cores are derived from or inspired by the ARM Cortex-A series “little” cores or Intel’s LP E-cores on Meteor Lake, which form a dedicated low-power island capable of running the entire OS while the main compute tile is power-gated. Another is that they are an offshoot of AMD’s own “dense” core family, perhaps a further-shrunk version of Zen 5c that can operate below 1 GHz. AMD’s patent filings have already explored SoC designs that include a primary computing complex alongside a secondary, always-on domain, so the idea is not without precedent.

Why Windows Users Should Care

Even though the patch lands in the Linux kernel, its impact reverberates directly into the Windows ecosystem. AMD’s Ryzen mobile processors dominate the modern laptop market, from thin-and-light Ultrabooks to convertible tablets and gaming handhelds. If future Ryzen chips come with three core types, Windows 11’s scheduler — and particularly the next major Windows release — will need explicit support to avoid performance missteps. Without such support, threads could land on the wrong core type, leading to sluggish UI, stuttering in games, or premature battery drain.

Microsoft and AMD have a history of deep co-engineering for hybrid architectures. When Intel introduced its Thread Director technology with Alder Lake, Microsoft retooled the scheduler for heterogeneous systems. AMD followed with its own CPPC-based solution later. The third core tier would likely trigger a similar collaboration, possibly resulting in new power profiles, additional Win32 API calls to query core capabilities, and updates to tools like Resource Monitor and Task Manager so power users can see which cores are handling what.

For end users, the payoff could be dramatic: a laptop that routinely hits 20+ hours of real-world battery life without sacrificing resume speed, or a gaming handheld that streams Netflix for twice as long because the low-power cores shoulder playback entirely. Desktop users might also benefit if AMD brings the technology to its APU line for mini-PCs or all-in-ones that prioritize silence and efficiency.

When Will We See These Cores?

Historically, AMD’s Linux enablement patches arrive roughly one kernel cycle ahead of the silicon’s appearance. That suggests a product announcement in late 2024 or early 2025, with shipping hardware by mid-2025. The most plausible candidates are the next generation of Ryzen AI mobile processors (perhaps codenamed “Strix Halo” or a successor), which are rumored to pack massive GPU power and could benefit from a low-power island to tame idle consumption. Alternatively, AMD might be targeting the handheld gaming PC market, where ASUS, Lenovo, and Valve are already customizing Ryzen Z1-series chips; a three-tier hybrid chip would be a natural fit for a device like a Steam Deck 2.

The patch also aligns with AMD’s broader move toward chiplet and tile-based designs. A low-power core cluster could reside on a separate compute tile that stays active when the main CPU and GPU tiles are off, enabling rapid wake times and persistent connectivity. This mirrors the disaggregated approach Intel has taken with Meteor Lake.

The Bigger Picture

The emergence of a low-power core type underscores how the battle for mobile supremacy is no longer fought on raw GHz alone. As AMD and Intel both race to match Apple’s M-series silicon in performance-per-watt, granular power management has become the new frontier. A three-tier CPU design, if executed well, could close the efficiency gap with Arm-based competitors while preserving x86 compatibility for the vast Windows software catalog.

What remains to be seen is whether AMD’s low-power cores will carry the full x86-64 instruction set or whether they will be stripped down, like Intel’s “LP” E-cores on Meteor Lake, which lack AVX2 support and require specific software tuning. If they are limited, application compatibility could become a headache for developers. Conversely, if they are fully ISA-compatible, the scheduler will have an easier time dynamically moving threads.

For now, the kernel patch is a tantalizing glimpse into AMD’s roadmap. It shows that the company is thinking beyond the simple big.LITTLE dichotomy toward a more flexible, power-optimized hierarchy. Windows enthusiasts should keep a close watch on the LKML and AMD’s official announcements over the coming months. The low-power core concept, once fully realized, could redefine what we expect from x86 laptops and handhelds — and how we configure Windows to take full advantage of them.

In the meantime, AMD’s current hybrid Ryzen laptops already deliver excellent battery life when configured properly. But the addition of a dedicated low-power tier promises to push those boundaries even further, making the always-connected, instant-on Windows experience a reality without the need for an Arm processor.