A recent teardown analysis of Huawei’s Kirin 9030 processor has delivered a jaw-dropping finding: SMIC’s N+3 fabrication process sports a local metal pitch of 32.5 nm, a figure that beats the 36 nm on Intel’s marquee 18A node. The revelation, which surfaced from a detailed report shared in semiconductor forums, challenges assumptions about the technology gap between China’s top foundry and the cutting edge of Western chip manufacturing. But while the number appears striking on paper, silicon success depends on far more than a single dimension.

The Kirin 9030 is Huawei’s latest flagship smartphone chip, and its appearance with a surprisingly tight metal pitch suggests that SMIC is wringing every ounce of capability from its deep-ultraviolet (DUV) lithography tools, even as U.S. export controls block access to extreme-ultraviolet (EUV) equipment. Intel’s 18A, which powers the recently unveiled Panther Lake CPUs for Windows laptops, is built with EUV and introduces RibbonFET gate-all-around transistors plus PowerVia backside power delivery. That such a node could cede a traditional scaling metric to a DUV-based Chinese alternative is both a testament to SMIC’s engineering ingenuity and a reminder that modern chip design involves a complex web of trade-offs.

Understanding Local Metal Pitch and Why It Matters

Local metal pitch refers to the minimum spacing between adjacent metal lines in the densest interconnect layers of a chip. It is one of the most critical indicators of a process node’s ability to route signals and power within a constrained area. A smaller metal pitch allows more wires in a given width, directly improving logic density and, potentially, performance by reducing the distance signals must travel.

For years, the semiconductor industry has chased ever-smaller pitches, moving from 28 nm in early nodes down to the low-20s in leading-edge 7 nm and 5 nm technologies. Intel’s original 10 nm node (now called Intel 7) featured a 36 nm minimum metal pitch, while TSMC’s 5 nm family uses pitches around 28 nm for the finest layers. Intel’s 4 nm and 3 nm nodes have tightened things further, but with 18A, Intel opted for a 36 nm minimum metal pitch, focusing instead on transistor architecture and power delivery innovations to boost overall performance and efficiency. That makes SMIC’s 32.5 nm claim on its N+3 process a genuine surprise—it is not just competitive with Intel’s latest, but theoretically allows a higher interconnect density in the local routing layers.

The Teardown: What We Know About Kirin 9030 and SMIC N+3

The details come from a technical teardown report that compared the Kirin 9030’s metal layers against known Intel 18A designs in Panther Lake CPUs. According to the findings, SMIC’s N+3 node uses a 32.5 nm minimum metal pitch for the critical local interconnects, while the Intel 18A part clocked in at 36 nm. The report did not disclose other crucial parameters such as cell height, gate pitch, or SRAM density, which collectively determine the true transistor density of a process.

SMIC’s N+3 is believed to be a refinement of its 7 nm-class N+2 node, which the company has been mass-producing for Huawei since mid-2023. Lacking EUV, SMIC relies on DUV immersion lithography with aggressive multi-patterning to achieve fine pitches. Industry experts estimate that N+3 may push transistor density above 100 million transistors per square millimeter (MTr/mm²), up from roughly 89–95 MTr/mm² on N+2. For comparison, Intel’s 18A is expected to deliver well over 200 MTr/mm², thanks to its high-NA EUV lithography, but that advantage comes more from transistor and cell-level scaling than from metal pitch alone. In other words, Intel trades off some interconnect density to optimize transistor performance and reduce overall power.

Intel 18A and Panther Lake: The Windows Laptop Benchmark

Intel’s 18A node represents the company’s ambitious bid to regain process leadership. Debuting in the Panther Lake platform, which will slot into next-generation Windows 11 laptops and desktops, 18A brings RibbonFET—Intel’s implementation of gate-all-around transistors—and PowerVia, which moves power delivery to the backside of the wafer. These innovations promise significant gains in performance per watt and allow Intel to pack more logic into a given area without necessarily pushing the absolute minimum metal pitch.

In the Panther Lake teardown that the report references, Intel’s 18A is seen using a 36 nm local metal pitch, consistent with Intel’s own disclosures. That is slightly looser than TSMC’s state-of-the-art N3P (around 30–32 nm), but Intel argues that its holistic design technology co-optimization (DTCO) offsets any density deficit. Early benchmarks of Panther Lake engineering samples suggest that Intel has indeed achieved competitive single-thread performance and battery life, placing it neck-and-neck with AMD and Qualcomm-based Windows laptops.

The fact that SMIC’s N+3 edges out Intel 18A on this one metric, then, is more a curiosity than a fundamental shift in the competitive landscape. Intel’s node is far more advanced in almost every other respect, from transistor architecture to lithography to yield management at scale.

The Real Gaps Beyond Metal Pitch

A single number can be misleading. Semiconductor process quality is multidimensional: transistor drive current, leakage, SRAM density, analog performance, yield, and production cost all play outsized roles. SMIC’s N+3, constrained to DUV, must employ quintuple or even sextuple patterning for critical layers, driving up wafer cost and cycle time while introducing defect risks. Yields, which SMIC and Huawei never officially disclose, are widely suspected to be well below the 80–90% typical of mature EUV-based nodes like Intel 18A or TSMC N5.

Moreover, the Kirin 9030 is a mobile SoC with a relatively modest die size—likely under 100 mm². For larger, high-performance chips like the 150–200 mm² CPU tiles found in Panther Lake, interconnect demand is greater, and the benefits of a tighter metal pitch could evaporate if other masks suffer from poor fidelity or alignment. Without EUV, SMIC also struggles to scale gate pitch and fin pitch to the levels needed for true density leadership. The Kirin 9030’s transistor performance, measured in megahertz per watt, almost certainly lags Intel’s by a wide margin, though exact comparisons are hindered by the lack of Windows-on-ARM support for Huawei’s chips.

Another critical chasm is the software and ecosystem support. Intel’s x86 architecture remains the cornerstone of the Windows world, while Huawei’s Kirin chips run Android or its own HarmonyOS. Even if SMIC could produce a chip that matches Intel in raw performance, the lack of a viable Windows on ARM stack for Huawei—due to U.S. bans—would keep it out of the laptop market that Windows enthusiasts care about most.

What It Means for China’s Semiconductor Trajectory

The revelation that SMIC can achieve a 32.5 nm metal pitch without EUV is a striking demonstration of China’s determination to circumvent export controls. Since 2020, SMIC has been barred from purchasing advanced lithography tools, yet it has managed to ship millions of 7 nm-class chips for Huawei’s Mate series phones. The N+3 node, likely used in the Kirin 9030 that powers the latest Mate handsets, shows that domestic process development is continuing—and at a pace that surprises many Western analysts.

Whether this matters for the Windows PC market depends on geopolitics and business decisions. If sanctions were ever relaxed, Huawei could conceivably design an ARM-based processor for Windows laptops and tap SMIC for fabrication. But that remains speculative. In the near term, Windows users will continue to see Intel, AMD, and Qualcomm battle for their dollars, with SMIC and Huawei playing no direct role.

Nevertheless, the technology demonstration is significant. It suggests that China’s domestic foundry may be narrowing the gap in certain structural dimensions, even if it cannot match the full-stack integration of Intel, TSMC, or Samsung. For the global semiconductor industry, it’s a wake-up call that innovation cannot be easily contained by export restrictions.

Conclusion

A teardown of Huawei’s Kirin 9030 offers a tantalizing headline: SMIC’s N+3 process has a tighter local metal pitch than Intel’s 18A. But semiconductor engineering is a discipline where the devil resides in the details. While SMIC has pulled off an impressive feat of DUV lithography, Intel’s 18A remains a generation ahead in transistor design, power delivery, and manufacturing maturity. For Windows laptop buyers, Panther Lake’s real-world performance will speak louder than any single dimensional metric. Still, the finding is a potent reminder that the global chip race is far from settled, and that China’s foundries are determined to push beyond the limits that sanctions attempt to impose.