A quiet corner of the Eindhoven High Tech Campus has become the focal point of a partnership that could reshape how chips power everything from data centers to lidar sensors. Dutch applied research institute TNO and lithography titan ASML have joined forces to drag indium phosphide photonic chips out of the pilot-line shadows and into the harsh light of high-volume manufacturing. The collaboration, announced this week, targets the stubborn gap between one-off laboratory triumphs and the repeatable, cost-effective processes fabs demand.
Photonic chips replace electrons with photons, modulating light rather than shuttling charge through copper traces. The payoff is bandwidth and energy efficiency that silicon electronics can’t touch. Indium phosphide (InP) is the prized substrate for these chips because it can both generate and detect light—a dual skill silicon lacks without exotic doping. That makes InP the material of choice for lasers, amplifiers, and photodetectors integrated directly onto a single die. Yet InP fabrication has remained notoriously fickle, with defect rates and wafer breakage scaring off all but the most specialized foundries.
TNO brings to the table its open-access InP pilot line, housed in a cleanroom at the High Tech Campus. The facility has already yielded functional photonic integrated circuits for telecom, medical imaging, and quantum sensing. ASML contributes its deep ultraviolet (DUV) lithography tools, metrology systems, and the process-control software that keeps its customers churning out billions of transistors on silicon. The goal is not to replace silicon CMOS but to bolt photonic functionality onto existing platforms through hybrid integration—placing InP chiplets alongside conventional processor cores.
“We are moving from an era of trying to prove that photonics works to proving that it can work at scale,” said a senior TNO engineer familiar with the agreement. “ASML’s understanding of holistic patterning—from mask design to wafer-level overlay—is exactly what we’ve been missing.” Neither party disclosed financial terms, but sources close to the deal indicated a multi-year roadmap with initial joint milestones in 2026.
Why the urgency now? Hyperscale data centers face a double bind: per-bit energy consumption must plummet while total traffic explodes. Optical interconnects already snake through server racks, but the electro-optical conversion happens in bulky pluggable modules that waste power and real estate. On-chip photonics promises to fold those functions onto the processor package, slashing latency and power by an order of magnitude. For Windows users, this translates to cloud services that feel more responsive, lower latency in Azure-based virtual desktops, and potentially photonic interposers in future Surface devices that pool compute and memory optically.
Microsoft has invested heavily in silicon photonics research for its data centers, but its efforts lean on silicon-based modulators that still require external light sources. A mature InP ecosystem would let Microsoft—and its competitors—source integrated lasers in the volumes needed to retrofit millions of servers. The TNO–ASML partnership could thus become a quiet enabler of Windows 365 and Azure Stack HCI performance jumps three or four generations from now.
Breaking down the collaboration. TNO will focus on the InP epitaxial wafers, handling the delicate deposition of indium, gallium, arsenide, and phosphide layers that form quantum wells for lasers and detectors. ASML steps in with its PAS 5500 and TWINSCAN DUV steppers, adapting optical proximity correction recipes to the peculiarities of InP films. InP crystals are more brittle and thermally sensitive than silicon, meaning standard chuck designs and overlay targets need rethinking. The partners plan to co-develop new alignment marks and wafer-handling protocols that maintain sub-50-nanometer overlay across a 100 mm InP wafer.
ASML’s YieldStar scatterometry tools will also get a workout. Measuring critical dimensions on transparent substrates is tricky; the partners are exploring multi-wavelength ellipsometry to extract grating profiles without destructive cross-sectioning. If they succeed, cycle times for process tweaks could shrink from weeks to hours—a prerequisite for any fab ramping to thousands of wafers per month.
The Eindhoven High Tech Campus. The choice of location is no accident. Often dubbed the smartest square kilometer in Europe, the campus already hosts over 200 companies, including Philips, NXP, and a cluster of photonics startups. A dedicated Photonics Integration Technology Center operates adjacent to TNO’s cleanroom, offering an on-site ecosystem for packaging and test. ASML’s Veldhoven headquarters sits less than 15 kilometers away, ensuring engineers can cycle between facilities in minutes. This geographic density mirrors the co-location advantages TSMC enjoys with its R&D partners in Hsinchu Science Park.
“Proximity is everything when you’re troubleshooting a new process,” explained a campus official. “An engineer can walk across the parking lot with a wafer, inspect it under a TEM, and be back at the stepper before lunch. That pace of learning is impossible if you have to ship samples to Switzerland or Singapore.”
The semiconductor backdrop. The partnership arrives as the chip industry grapples with the twilight of simple dimensional scaling. ASML’s extreme ultraviolet (EUV) tools enable 3 nm and 2 nm nodes, but the performance uplift per shrink is diminishing. System-level gains increasingly come from packaging—connecting chiplets horizontally or stacking them vertically. Photonic interposers represent the logical next step: an optical layer sandwiched between logic and memory dies that ferries terabits of data without the heat and resistance of copper traces.
Intel has demonstrated an eight-wavelength silicon photonic transmitter, and Ayar Labs is sampling optical I/O chiplets to early customers. But both approaches still rely on external laser sources. A TNO–ASML InP flow could yield on-chip lasers in standard BGA packages, eliminating the fiber pigtails that complicate assembly. If the partnership delivers, it might ignite a platform shift akin to the move from discrete transistors to integrated circuits.
Critical hurdles. None of this will come easily. InP defect densities remain orders of magnitude above silicon CMOS levels. A single dark-line defect in a laser cavity can kill a device, and such defects multiply under the thermal and electrical stress of operation. The partners will need to marry ASML’s defect inspection algorithms with TNO’s materials know-how to root out causes at the crystal growth stage.
Cost is another iceberg. An InP wafer today can cost ten times a silicon wafer of similar diameter, and the specialized processing steps—etching III-V materials with highly toxic chemicals, depositing gold contacts, and cleaving facets for laser mirrors—require dedicated tooling that fabs amortize over low volumes. The partnership’s unstated mission is to carve out a “good enough” process flow that uses as much standard silicon equipment as possible, avoiding the need for a greenfield photonics-only fab.
There’s also the question of standards. For photonic chips to slot into the PC ecosystem, interfaces like PCIe and CXL must be adapted for optical links. Microsoft has been active in the CXL Consortium, pushing an optical extension that would allow Windows machines to access pooled memory across a rack using light. If the TNO–ASML collaboration yields cost-effective chip-to-chip optical engines, it could accelerate the ratification of those standards.
Windows and the photonic future. While consumer laptops won’t pack on-chip lasers for years, the trickle-down effects could be profound. Edge AI accelerators for Windows on Arm devices could use optical interconnects to stream sensor data to neural processing units without bogging down main memory. Mixed-reality headsets—long challenged by the bandwidth needed for high-resolution waveguide displays—might adopt photonic micro-displays built on InP emitter arrays. The underlying theme is disaggregation: pulling apart the monolithic PC architecture and reassembling it with light as the universal bus.
Microsoft’s own Azure CTO has spoken publicly about the “optical data center” as a destination rather than a detour. With Copilot+ workloads demanding ever more data movement between GPUs and memory, the cost of electrical SERDES hits a wall. Photonic interposers could allow a single rack to house 64 GPUs sharing a coherent memory pool, all linked by InP laser rings. That would make training a 10-trillion-parameter AI model feasible without the networking headaches that plague current clusters.
What the analysts say. Chip industry watcher Dylan Patel notes that “ASML rarely wades into materials-specific partnerships unless it sees a credible path to tool sales in the hundreds-of-units range.” That suggests the company expects photonics to graduate from niche to mainstream within this decade. Research firm Yole Intelligence projects the silicon photonics market alone to surpass $5 billion by 2028; InP modules for telecom will add another $2 billion. If the partnership cracks the scalability problem, those numbers could prove conservative.
“This is not a science project,” said a semiconductor equipment analyst who requested anonymity. “ASML is placing a very calculated bet that the same machine-learning-based overlay and focusing algorithms that made EUV manufacturable can tame InP. And TNO gets something priceless: an industrial-quality lithography partner that can turn its research into a foundry-ready PDK [process design kit].”
Broader implications for the Netherlands. The pact reinforces the Brainport Eindhoven region’s ambition to become Europe’s semiconductor anchor alongside Intel’s Magdeburg fab and TSMC’s Dresden venture. The Dutch government has earmarked €2.3 billion for the microchip sector through Project Beethoven, and while TNO is a public-private entity, the alignment with ASML—the country’s most valuable tech company—creates a gravity well for talent and investment.
The partnership also serves as a hedge against geopolitical fracturing. With China aggressively funding its own InP photonics research at institutes like the Shanghai Institute of Microsystem and Information Technology, a European supply chain for photonic components becomes strategically important. ASML’s tools are already subject to export controls; ensuring that the next wave of photonic intellectual property stays in friendly hands is a quiet but real undercurrent.
Timeline and milestones. The first year will focus on transferring TNO’s pilot-line recipes to ASML’s process qualification tools at Veldhoven. By mid-2026, the partners aim to demonstrate a laser array with sub-micron pitch uniformity across a full 100 mm wafer. If that succeeds, a multi-project wafer shuttle will follow, allowing startups and research groups to submit designs for shared fabrication runs—lowering the barrier to entry exponentially.
“Think of it as the MOSIS of photonics,” the TNO engineer said, referring to the iconic silicon prototyping service that fueled the 1980s VLSI revolution. “You design a ring resonator or an optical switch, upload your GDS file, and eight weeks later you have packaged dice. That’s the vision.”
The impact on Windows development may take five years to materialize, but the seeds are being planted now. Device manufacturers like Dell and HP pay close attention to component roadmaps that promise step-function gains in battery life or display performance. A low-power optical interconnect could make always-connected Windows laptops genuinely compelling, solving the days-long battery life dream that Intel’s Silicon Photonics group once touted.
Conclusion. TNO and ASML’s collaboration is a signal flare for the photonic semiconductor era. It marries deep materials research with the manufacturing muscle that only a few companies on Earth possess. For Windows enthusiasts, the payoff lies in the infrastructure that will power the next decade of AI, cloud, and on-device compute—all running on beams of light rather than streams of electrons. The hard work begins now, on a campus in Eindhoven, where two Dutch heavyweights are redrawing the boundaries of what’s possible on a chip.