Seoul National University researchers have demonstrated a CMOS-compatible ferroelectric memory semiconductor that for the first time combines probabilistic sampling and deterministic AI computation on the same device, a breakthrough that could reshape edge AI accelerators and bring more powerful on-device intelligence to Windows Copilot+ PCs. The team, led by Professor Jong-Ho Lee, announced on May 19, 2026 that their novel ferroelectric field-effect transistor (FeFET) memory cell can perform both the unpredictable, sample-based calculations required for generative AI and the precise matrix multiplications that underpin conventional neural networks—all within a single, mass-production-friendly structure.

The advance addresses a fundamental bottleneck in current AI hardware: the need to shuttle data between separate memory and processing units for different types of computation. By embedding probabilistic and deterministic operations directly into the memory array, the SNU device slashes energy consumption and latency, making it an ideal candidate for the neural processing units (NPUs) that Microsoft and its hardware partners are already integrating into the latest Windows laptops.

Why Ferroelectric Memory Matters Now

Ferroelectric memory has long tantalized chipmakers with its non-volatile nature, fast switching speeds, and low power draw. Unlike charge-based DRAM or flash, FeFETs rely on a ferroelectric gate dielectric—commonly hafnium oxide (HfO₂) doped with elements like zirconium or silicon—that retains polarization states without a constant power supply. This gives them the persistence of flash and the speed approaching DRAM, while fitting neatly into standard CMOS logic processes.

What sets the SNU demonstration apart is how it harnesses the inherent stochasticity of ferroelectric switching. When a FeFET is programmed, the domain nucleation and growth in the ferroelectric layer are fundamentally random processes. Traditional memory design seeks to suppress this variability; Professor Lee’s team instead exploits it to generate true random numbers and perform probabilistic sampling directly within the memory cell. The same cell can later be operated in a deterministic mode, using precise voltage pulses to store binary weights for multiply-accumulate operations—the backbone of AI inference.

This dual-mode operation is achieved through a carefully engineered gate stack and a read-out scheme that distinguishes between the high and low threshold voltage states even when partial switching introduces stochasticity. In deterministic mode, a strong programming pulse ensures complete polarization reversal, yielding clearly separated Vth levels. For probabilistic sampling, a weaker pulse triggers partial switching, leaving the cell in a metastable state whose final value depends on thermal noise and process variations. By measuring the current through multiple cells, the array can generate samples from a Boltzmann distribution—a critical requirement for energy-based models like restricted Boltzmann machines and deep belief networks, as well as for emerging Bayesian neural networks.

Unifying AI Workloads on a Single Substrate

Modern AI applications are bifurcating into two computational paradigms. Deterministic inference—image classification, object detection, natural language understanding in voice assistants—relies on precise, repeatable tensor operations. Probabilistic models, essential for generative AI, recommendation systems, and uncertainty quantification, need to sample from complex distributions. Today’s accelerators handle these with separate hardware blocks: deterministic matrix engines alongside pseudo-random number generators or dedicated probabilistic circuits. The SNU memory cell collapses both into the same physical transistor array.

During deterministic mode, the FeFET array functions as a dense in-memory computing matrix. Stored weights define the conductance of each cell, and when input voltages are applied to the word lines, the resulting currents on the bit lines directly produce dot-product results. No data movement between RAM and ALU is required. The probabilistic mode operates differently: by controlling the pulse amplitude and duration, the array generates a population of partially switched cells whose collective current encodes a sample from a target probability distribution. This is akin to performing Markov chain Monte Carlo sampling directly in the analog domain, at speeds and densities impossible with digital circuits.

Professor Lee’s team reportedly validated the concept on a 4kb array fabricated in a commercial 28nm CMOS process, demonstrating both accurate vector-matrix multiplication and low-discrepancy sampling from Gaussian and binomial distributions. The energy efficiency for sampling was measured at less than 1 femtojoule per sample, while deterministic multiply-accumulate reached 1 TOPS/W—figures that are competitive with leading-edge NPU designs but with the flexibility to handle both workload types without reconfiguration overhead.

Implications for Windows Copilot+ PCs and Edge AI

Microsoft’s Copilot+ brand, launched in 2024, established a new baseline for AI-accelerated Windows notebooks, requiring a dedicated NPU with at least 40 TOPS of throughput. Qualcomm’s Snapdragon X Elite, Intel’s Lunar Lake, and AMD’s Ryzen AI 300 series all integrate such engines, but they remain specialized for deterministic inference. As Windows increasingly incorporates generative features—recall-enhanced search, real-time captioning, Studio Effects, and small language models that run locally—the ability to efficiently run probabilistic models on-device becomes critical.

The SNU FeFET memory could fundamentally alter NPU design. Instead of a dedicated inference engine coupled with a separate pseudo-random number generator and sampling logic, a future Copilot+ NPU might incorporate a unified FeFET compute-memory block that handles both generative sampling and deterministic inference at near-memory bandwidth. This would reduce silicon area, lower power, and simplify programming models, as the same memory structure serves dual duty.

It also opens the door to more sophisticated on-device AI that currently requires cloud offloading. Bayesian deep learning, which offers calibrated uncertainty estimates alongside predictions, has been too computationally expensive for mobile SoCs. With native probabilistic sampling, a laptop could run Bayesian vision models that refuse to classify an unfamiliar object rather than hallucinating a label. Similarly, generative features like Stable Diffusion image synthesis or on-the-fly style transfer could execute locally with minimal battery impact, preserving privacy and responsiveness.

Competitive Edge: Where FeFET Stands in the Memory-AI Race

The memory landscape is crowded with candidates aiming to break the von Neumann bottleneck. Resistive RAM (ReRAM) and magnetic RAM (MRAM) have seen commercial deployment as embedded non-volatile memory and, in the case of MRAM, as a cache replacement. Both offer in-memory computing possibilities, but FeFET holds distinct advantages for a unified AI memory. ReRAM’s stochastic switching can also be used for random number generation, but its filamentary conduction mechanism leads to wide variability and endurance issues. MRAM requires high write currents and suffers from limited ON/OFF ratios, making dense analog computation difficult.

Ferroelectric memory, particularly HfO₂-based FeFETs, has demonstrated million-cycle endurance, nanosecond switching, and retention beyond 10 years at elevated temperatures. More importantly, its compatibility with established high-k metal gate CMOS flows has enabled early adoption. GlobalFoundries offers FeFET as an embedded NVM option on its 22FDX platform, and Intel has explored ferroelectric RAM for low-power caches. But until now, no one had combined deterministic and probabilistic operation in a single cell.

The SNU work also complements recent academic breakthroughs in FeFET-based compute-in-memory. A 2024 paper in Nature Electronics demonstrated a FeFET array performing transformer attention with high accuracy. Another group at the University of California, Berkeley, used FeFETs for one-shot learning through partial polarization. The Seoul team’s innovation ties these threads together, showing that the same cell and array architecture can toggle between two fundamental computing modes with no hardware changes.

Manufacturing Readiness and the Path to Productization

Professor Lee’s emphasis on CMOS compatibility is no accident. The semiconductor industry moves slowly, and a new memory technology must demonstrate viability on existing 300mm lines to attract foundry interest. The 28nm node used in the prototype is a mature, high-yield process widely available at TSMC, Samsung, and UMC. Scaling the design to advanced nodes—7nm, 5nm, or beyond—presents challenges, primarily because ferroelectric properties in ultra-scaled HfO₂ films can degrade. However, SNU reported successful integration without exotic materials or process steps, relying on standard ALD deposition and thermal budgets below 500°C.

Industry analysts note that if SNU’s findings hold at production scale, the technology could be grafted onto existing NPU designs as a drop-in memory block. Microsoft’s direct involvement with Qualcomm and Intel on Windows AI requirements could accelerate adoption, especially if the software giant’s DirectML or ONNX Runtime APIs can abstract the dual-mode hardware beneath a unified developer interface.

Patents related to the work have been filed, and SNU is in talks with several Korean and global chipmakers to license the technology. A startup spun out from the lab, tentatively named FerroAI Semiconductor, aims to deliver FeFET accelerator IP for SoC integration by early 2028.

Real-World Impact on Windows Users

For Windows enthusiasts, the near-term benefit will be longer battery life and quieter fanless designs in thin-and-light laptops. AI tasks that today spin up the NPU to full power could run in the background on a FeFET-based memory array consuming milliwatts. The long-term vision is more transformative: a Copilot+ PC that continuously runs a probabilistic personal assistant model, learning user habits, anticipating needs, and safeguarding data with uncertainty-aware security algorithms, all without phoning home to the cloud.

Developers would gain access to a new class of AI primitives. Instead of coding separate pipelines for inference and generation, they could call a single “sample_infer” API that handles both, letting the hardware decide the most efficient execution mode. Game engines could employ real-time probabilistic AI for non-player characters that adapt and surprise, or for real-time physics simulations that require Monte Carlo path tracing.

Challenges and the Road Ahead

Despite the promise, hurdles remain. The stochastic behavior that enables probabilistic sampling must be tightly controlled—device-to-device variations could lead to sampling bias. The team demostrated a variation-aware training method that compensates, but its robustness across temperature and aging needs validation. Endurance, while acceptable for inference, may limit online learning applications that require frequent weight updates. And integrating FeFET memory onto a logic die alongside CPUs and GPUs adds process complexity that could increase wafer cost.

Nevertheless, the Seoul demonstration arrives at a time when the AI industry is desperate for more efficient hardware. Data center GPUs have made generative AI ubiquitous, but the energy costs are unsustainable, and user desire for private, offline AI is growing. A memory technology that unites the stochastic heart of creativity with the deterministic muscle of reasoning could be what finally brings true AI ubiquity to the Windows PC. For now, all eyes are on SNU’s follow-up work and the first silicon from its commercial partners—expected to appear at the International Solid-State Circuits Conference early next year.

Conclusion: A Step Toward Thinking Machines on Every Desk

The line between memory and compute continues to blur, and the SNU FeFET device pushes it further into the analog domain. By embracing noise rather than eliminating it, Professor Lee’s team has turned a long-standing challenge into an asset, crafting a memory cell that reflects the dual nature of intelligence itself—precise yet unpredictable. For Windows users, the breakthrough could mean that the next Copilot+ laptop on their desk doesn’t just execute AI commands; it begins to think with a native, silicon-level appreciation for uncertainty. That’s a future worth watching.